LazyFTL: a page-level flash translation layer optimized for NAND flash memory

Flash is a type of electronically erasable programmable read-only memory (EEPROM), which has many advantages over traditional magnetic disks, such as lower access latency, lower power consumption, lack of noise, and shock resistance. However, due to its special characteristics, flash memory cannot be deployed directly in the place of traditional magnetic disks. The Flash Translation Layer (FTL) is a software layer built on raw flash memory that carries out garbage collection and wear leveling strategies and hides the special characteristics of flash memory from upper file systems by emulating a normal block device like magnetic disks. Most existing FTL schemes are optimized for some specific access patterns or bring about significant overhead of merge operations under certain circumstances. In this paper, we propose a novel FTL scheme named LazyFTL that exhibits low response latency and high scalability, and at the same time, eliminates the overhead of merge operations completely. Experimental results show that LazyFTL outperforms all the typical existing FTL schemes and is very close to the theoretically optimal solution. We also provide a basic design that assists LazyFTL to recover from system failures.

[1]  Young-Jin Kim,et al.  LAST: locality-aware sector translation for NAND flash memory-based storage systems , 2008, OPSR.

[2]  Dongkun Shin,et al.  Adaptive Log Block Mapping Scheme for Log Buffer-based FTL ( Flash Translation Layer ) , 2009 .

[3]  Dongkun Shin,et al.  KAST: K-associative sector translation for NAND flash memory in real-time systems , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[4]  Tei-Wei Kuo,et al.  An Efficient B-Tree Layer for Flash-Memory Storage Systems , 2003, RTCSA.

[5]  Ramesh K. Sitaraman,et al.  Lazy-Adaptive Tree: An Optimized Index Structure for Flash Devices , 2009, Proc. VLDB Endow..

[6]  Chanik Park,et al.  A Re-configurable FTL (Flash Translation Layer) Architecture for NAND Flash based Applications , 2007, 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07).

[7]  Jin-Soo Kim,et al.  mu-tree: an ordered index structure for NAND flash memory , 2007, EMSOFT.

[8]  Antony I. T. Rowstron,et al.  Write off-loading: Practical power management for enterprise storage , 2008, TOS.

[9]  Tei-Wei Kuo,et al.  Efficient identification of hot data for flash memory storage systems , 2006, TOS.

[10]  Suman Nath,et al.  FlashDB: Dynamic Self-tuning Database for NAND Flash , 2007, 2007 6th International Symposium on Information Processing in Sensor Networks.

[11]  Sang Lyul Min,et al.  A space-efficient flash translation layer for CompactFlash systems , 2002, IEEE Trans. Consumer Electron..

[12]  Sang-Won Lee,et al.  Design of flash-based DBMS: an in-page logging approach , 2007, SIGMOD '07.

[13]  Heeseung Jo,et al.  A superblock-based flash translation layer for NAND flash memory , 2006, EMSOFT '06.

[14]  Bingsheng He,et al.  Tree indexing on solid state drives , 2010, Proc. VLDB Endow..

[15]  Jin-Soo Kim,et al.  μ-FTL:: a memory-efficient flash translation layer supporting multiple mapping granularities , 2008, EMSOFT '08.

[16]  Sivan Toledo,et al.  Algorithms and data structures for flash memories , 2005, CSUR.

[17]  Sang-Won Lee,et al.  A log buffer-based flash translation layer using fully-associative sector translation , 2007, TECS.

[18]  Dong-Ho Lee,et al.  HFTL: hybrid flash translation layer based on hot data identification for flash memory , 2009, IEEE Transactions on Consumer Electronics.

[19]  Tony Givargis,et al.  Performance improvement of block based NAND flash translation layer , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[20]  Tei-Wei Kuo,et al.  An efficient management scheme for large-scale flash-memory storage systems , 2004, SAC '04.

[21]  Seung Ryoul Maeng,et al.  FTL design exploration in reconfigurable high-performance SSD for server applications , 2009, ICS.

[22]  Youngjae Kim,et al.  DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings , 2009, ASPLOS.

[23]  Kyu Ho Park,et al.  JFTL: A flash translation layer based on a journal remapping for flash memory , 2009, TOS.

[24]  Chanik Park,et al.  A Re-configurable FTL (Flash Translation Layer) Architecture for NAND Flash based Applications , 2007, IEEE International Workshop on Rapid System Prototyping.