System on a FPGA Virtual Concatenation

This paper presents the study and implementation of a novel architecture for a virtual concatenation circuit using the NIOS soft core embedded processor on a FPGA (APEX). The architecture is optimised for rapid adaptation of the virtual concatenation core by exploiting the reconfigurable properties of the FPGA technology and the programmable properties of embedded processors. This synergy provides a hardware efficient implementation of hitless re-configuration of transmission paths and the rapid adaptation of the architecture for a wide range of data transmission products to keep pace with product and standard migrations.