Exploiting data-redundancy in reliability-aware networked embedded system design

This paper presents a system-level design methodology for networked embedded systems that exploits existing data-redundancy to increase their reliability. The presented approach not only supports a reliability-aware embedded system design from scratch, but also enables the redesign of existing systems to increase the reliability with a minimal communication overhead. The proposed approach contributes (a) algorithms to automatically identify inherent data-redundancy and (b) an automatic design space exploration that is capable of exploiting the revealed data-redundancy. A symbolic analysis is presented that quantifies the reliability of a system, enabling the usage of reliability as one of multiple conflicting optimization objectives. The proposed approach is applied to a realworld case study from the automotive area, showing a significantly increased reliability with a negligible communication overhead.

[1]  David W. Coit,et al.  Reliability optimization of series-parallel systems using a genetic algorithm , 1996, IEEE Trans. Reliab..

[2]  Paolo Pavan,et al.  Improving the reliability and safety of automotive electronics , 1993, IEEE Micro.

[3]  Hermann Kopetz,et al.  Tolerating Arbitrary Node Failures in the Time-Triggered Architecture , 2001 .

[4]  Petru Eles,et al.  Synthesis of Fault-Tolerant Embedded Systems , 2008, 2008 Design, Automation and Test in Europe.

[5]  Mahmut T. Kandemir,et al.  Reliability-centric high-level synthesis , 2005, Design, Automation and Test in Europe.

[6]  Mary Jane Irwin,et al.  Reliability-aware co-synthesis for embedded systems , 2004 .

[7]  Petru Eles,et al.  Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints , 2008, 2008 Design, Automation and Test in Europe.

[8]  Martin Lukasiewycz,et al.  Symbolic Reliability Analysis and Optimization of ECU Networks , 2008, 2008 Design, Automation and Test in Europe.

[9]  Herbert Hanselmann,et al.  Challenges in automotive software engineering , 2008, ICSE Companion '08.

[10]  Randal E. Bryant,et al.  Symbolic Boolean manipulation with ordered binary-decision diagrams , 1992, CSUR.

[11]  Martin Lukasiewycz,et al.  SAT-decoding in evolutionary algorithms for discrete constrained optimization problems , 2007, 2007 IEEE Congress on Evolutionary Computation.

[12]  Yeqiong Song,et al.  Evaluating quality of service and behavioral reliability of steer-by-wire systems , 2003, EFTA 2003. 2003 IEEE Conference on Emerging Technologies and Factory Automation. Proceedings (Cat. No.03TH8696).

[13]  Arshad Jhumka,et al.  A dependability-driven system-level design approach for embedded systems , 2005, Design, Automation and Test in Europe.

[14]  Martin Lukasiewycz,et al.  Interactive presentation: Reliability-aware system synthesis , 2007 .

[15]  Bruno Gaujal,et al.  Optimal replica allocation for TTP/C based systems , 2003 .

[16]  Thorsten Gerke,et al.  An Automated Model Based Design Flow for the Design of Robust FlexRay™ Networks , 2008 .

[17]  Alan Burns,et al.  Calculating controller area network (can) message response times , 1994 .

[18]  Martin Lukasiewycz,et al.  Reliability-Aware System Synthesis , 2007 .

[19]  Martin Lukasiewycz,et al.  Reliability-Aware System Synthesis , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[20]  Ying Zhang,et al.  Energy-aware deterministic fault tolerance in distributed real-time embedded systems , 2004, Proceedings. 41st Design Automation Conference, 2004..

[21]  John P. Lehoczky,et al.  Timing Analysis for Fixed-Priority Scheduling of Hard Real-Time Systems , 1994, IEEE Trans. Software Eng..

[22]  Antoine Rauzy,et al.  New algorithms for fault trees analysis , 1993 .