High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model

In this work, we provide an overview of out high-level synthesis framework PARO. PARO is targeted at data flow dominant algorithms where most of the computational load lies in loop nests, defined by affine expressions. In Zn these loop definitions can be interpreted as half-spaces, which intersect to form convex polyhedra around the sets of loop iterations. Hence, we employ the polyhedron model to analyze and restructure these algorithms to derive highly parallel and energy efficient implementations on massively parallel architectures. Specifically, in this work, we discuss the implementation of dedicated FPGA accelerators and showcase the capabilities of out framework for the development of a range image conditioning pipeline for smart range sensing cameras.