Modeling Interconnects for Post-CMOS Devices and Comparison With Copper Interconnects

Power dissipation in charge-based technology is the biggest roadblock toward miniaturizing circuits. Quantum-mechanical tunneling and subthreshold leakage current will ultimately limit scaling of silicon field-effect transistors. To continue Moore's law scaling, it is imperative that devices working with a state variable other than electron charge are sought for. Examples of alternate state variables include electron spins, pseudo-spins in graphene, direct and indirect excitons, plasmons, and phonons. At the same time, interconnection aspects of devices utilizing novel state variables must be considered early on. This paper provides a framework to quantify energy dissipation in interconnects for novel state variables. Models for energy per bit are then used along with previously derived models for delay of interconnects for novel state variables to compare performance and energy dissipation of novel interconnects with complementary metal-oxide-semiconductor (CMOS) interconnects. Comparison results provide important insights into material, device, and circuit implications of post-CMOS technologies.