Implementing of fast graphic functions in FPGA programmable logic

Abstract The paper deals with a possibility of using the FPGA architecture for implementing the fast simple 2D graphics with minimum of logic resources. The basis of that work was published in (Kasik, 2008) and since the time it has been extended with polar to rectangular coordinates computing for graphic 2D objects. The presented logic design shapes the graphics adapter, which is generally built of combinatorial logic without video-memory. The graphics adapter is designed for programmable FPGA devices and their specific logic resources, especially fast parallel multipliers.