TorusBFS : A Novel Message-passing Parallel Breadth-First Search Architecture on FPGAs

Graphs are a fundamental data structure used extensively in numerous domains. In graph-based applications, Breadth-First Search (BFS) is a key component which suffers from long latency of memory accesses. In this paper, we present a novel message passing parallel BFS architecture namely TorusBFS on field-programmable gate array (FPGA). By utilizing the on-chip memories to store the visitation status of vertices and to implement the current/next queue, our architecture reduces the accesses to the off-chip memories. We also present a on-chip 2-D torus message passing structure to reduce latencies of exchanging information among processing elements (PEs). Limited to the inefficient random write accesses to the off-chip memories, the experimental results show that our architecture on a single FPGA achieves relative lower performance compared with related works based on Convey HC1/HC-2 platforms. Nevertheless, our TorusBFS is the first architecture that can be easily extended to multiple FPGAs in a distributed environment. Keywords-Breadth-First Search; Graph500; FPGA; Message Passing