The application of Taguchi method on the robust optimization of p-FinFET device parameters

Determining the exact device parameter for a particular transistor is crucial in order to ensure the device is operating at their best possible conditions. This paper discusses the application of Taguchi method on device parameter design for a 7nm germanium p-FinFET with optimization using design of experiments. In this work, the Sentaurus Simulator is used as the medium of simulation and analysis. The Taguchi method was implemented to determine the most appropriate combination of factors for robust device performance using orthogonal arrays, signal-to-noise ratio as well as Pareto analysis of variance as the quality characteristic of choices. The factors involved in the design of experiments include the length and height of the fin as well as the width of the fin at the top region. The on-state current and off-state current were considered using these methods by applying larger the better and smaller the better characteristics respectively. Using Taguchi's robust performance signal-to-noise ratio and Pareto analysis of variance, the combination of parameters with high on-current and low off-current were obtained. It is observed that with fin length of 8nm, height of 35nm and width of 7nm, the best performance in terms of on-current for p-FinFET can be achieved with the values of 1.8847mA. On the contrary, with dimensions fin length of 15nm, height of 25nm and width of 2nm can leads to best performance in terms of off-current with the values of 26.7nA.

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