Meeting delay constraints in DSM by minimal repeater insertion

We address the problem of inserting repeaters, selected from a library, at feasible locations in a placed and routed network to meet user-specified delay constraints for deep submicron (DSM) technology. We use minimal repeater area by taking advantage of slacks available in the network. Specifically, we transform the problem into an unconstrained optimization problem and solve it by iterative local refinement. We show that the optimal repeater locations and sizes that locally minimize the objective function in the unconstrained problem can be efficiently computed. We have implemented our algorithm and tested it on a set of benchmarks; experimental results are promising.

[1]  L.P.P.P. van Ginneken,et al.  Buffer placement in distributed RC-tree networks for minimal Elmore delay , 1990 .

[2]  Hai Zhou,et al.  Simultaneous routing and buffer insertion with restrictions on buffer locations , 1999, DAC '99.

[3]  Yehea I. Ismail,et al.  Effects of inductance on the propagation delay and repeater insertion in VLSI circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[4]  Kurt Keutzer,et al.  Getting to the bottom of deep submicron , 1998, ICCAD '98.

[5]  Tom Dillinger,et al.  Delay bounded buffered tree construction for timing driven floorplanning , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[6]  Godwin C. Ovuworie,et al.  Mathematical Programming: Structures and Algorithms , 1979 .

[7]  Charles J. Alpert,et al.  Buffer insertion with accurate gate and interconnect delay computation , 1999, DAC '99.

[8]  A. Kahng,et al.  A new approach to simultaneous buffer insertion and wire sizing , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[9]  Jason Cong,et al.  Buffered Steiner tree construction with wire sizing for interconnect layout optimization , 1996, Proceedings of International Conference on Computer Aided Design.

[10]  Martin D. F. Wong,et al.  Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[11]  W. C. Elmore The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[12]  Hai Zhou,et al.  An efficient buffer insertion algorithm for large networks based on Lagrangian relaxation , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

[13]  Charles J. Alpert,et al.  Wire segmenting for improved buffer insertion , 1997, DAC.

[14]  Jason Cong,et al.  Performance optimization of VLSI interconnect layout , 1996, Integr..

[15]  Charlie Chung-Ping Chen,et al.  Noise-aware repeater insertion and wire-sizing for on-chip interconnect using hierarchical moment-matching , 1999, DAC '99.

[16]  Chung-Kuan Cheng,et al.  Optimal wire sizing and buffer insertion for low power and a generalized delay model , 1995, ICCAD.

[17]  Ravindra K. Ahuja,et al.  Network Flows: Theory, Algorithms, and Applications , 1993 .

[18]  Kurt Keutzer,et al.  Getting to the bottom of deep submicron II: a global wiring paradigm , 1999, ISPD '99.