论文信息 - Effect of Threshold-Voltage Instability on SiC DMOSFET Reliability

Effect of Threshold-Voltage Instability on SiC DMOSFET Reliability

The instability of the threshold voltage in SiC power DMOSFETs due to gate-bias stress and ON-state stress is a potential reliability issue, although the effects can be mitigated if the threshold voltage is set with enough positive margin so that no increase in OFF-state leakage occurs. In this case, the primary effect will be to increase the ON-state resistance by about five percent, which should be tolerable for power converter applications. Subthreshold-slope analysis of slower parameter-analyzer results reveal similar instabilities to those of fast I-V measurements.

N. Goldsman | D. Habersat | R. Green | Aivars Lelis

[1] Neil Goldsman,et al. Bias Stress-Induced Threshold-Voltage Instability of SiC MOSFETs , 2006 .

[2] G. Duscher,et al. Transition layers at the SiO2∕SiC interface , 2008 .

[3] Anant K. Agarwal,et al. Hall Mobility of the Electron Inversion Layer in 6H-SiC MOSFETs , 2000 .

[4] R. Hayward. Stress , 2005, The Lancet.

[5] Qamar Ul Wahab,et al. High-carbon concentrations at the silicon dioxide–silicon carbide interface identified by electron energy loss spectroscopy , 2000 .

[6] J. Suehle,et al. Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements , 2008, IEEE Transactions on Electron Devices.

[7] N. Goldsman,et al. Characterization of Transient Gate Oxide Trapping in SiC MOSFETs Using Fast $I$–$V$ Techniques , 2008, IEEE Transactions on Electron Devices.