Comparative Simulation Study of the Different Sources of Statistical Variability in Contemporary Floating-Gate Nonvolatile Memory

For the first time, a comprehensive comparative study of the impact of different sources of statistical variability in nonvolatile memory (NVM) has been carried out using the 3-D numerical simulation of large statistical ensembles and approaches based on the impedance-field method. Results of the threshold voltage variability in a template 32-nm floating-gate NVM subject to random discrete dopants (RDD), line edge roughness, oxide thickness fluctuations, polysilicon granularity, and interface trapped charge (ITC) are presented. The relative impact of each source of statistical variability has been highlighted, with RDD being identified as the dominant source and ITC as the next most dominant source. Based on the simulation of statistical samples of 1000 microscopically different devices, the shape and spread of the statistical distribution associated with each individual and combined sources of variability have been found to significantly be different from a normal distribution, particularly within the tails that may have significant implications for design and yield. Finally, an ensemble of 59 000 devices is used to characterize the combined impact of all sources of variability.

[1]  A. Lacaita,et al.  First evidence for injection statistics accuracy limitations in NAND Flash constant-current Fowler-Nordheim programming , 2007, 2007 IEEE International Electron Devices Meeting.

[2]  Petru Andrei,et al.  Quantum Mechanical Effects on Random Oxide Thickness and Doping Fluctuations in Ultrasmall Semiconductor Devices , 2003 .

[3]  Asen Asenov,et al.  Statistical enhancement of combined simulations of RDD and LER variability: What can simulation of a 105 sample teach us? , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[4]  A. Asenov,et al.  Impact of single charge trapping in nano-MOSFETs-electrostatics versus transport effects , 2005, IEEE Transactions on Nanotechnology.

[5]  A. Asenov,et al.  Statistical Simulation of Progressive NBTI Degradation in a 45-nm Technology pMOSFET , 2010, IEEE Transactions on Electron Devices.

[6]  M. Hane,et al.  Atomistic 3D process/device simulation considering gate line-edge roughness and poly-Si random crystal orientation effects [MOSFETs] , 2003, IEEE International Electron Devices Meeting 2003.

[7]  A. Asenov,et al.  Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs , 2006, IEEE Transactions on Electron Devices.

[8]  R. Balasubramaniam,et al.  Signal Amplitudes in Sub 100 nm ( Decanano ) MOSFETs : A 3 D ‘ Atomistic ’ Simulation Study , 2000 .

[9]  H. Watanabe,et al.  Statistics of Grain Boundaries in Polysilicon , 2007, IEEE Transactions on Electron Devices.

[10]  A. Visconti,et al.  Giant Random Telegraph Signals in Nanoscale Floating-Gate Devices , 2007, IEEE Electron Device Letters.

[11]  A. Visconti,et al.  Comprehensive Analysis of Random Telegraph Noise Instability and Its Scaling in Deca–Nanometer Flash Memories , 2009, IEEE Transactions on Electron Devices.

[12]  D Reid,et al.  Understanding LER-Induced MOSFET $V_{T}$ Variability—Part I: Three-Dimensional Simulation of Large Statistical Samples , 2010, IEEE Transactions on Electron Devices.

[13]  Asen Asenov,et al.  Impact of intrinsic parameter fluctuations in decanano MOSFETs on yield and functionality of SRAM cells , 2005 .

[14]  A. Asenov,et al.  Poly-Si-Gate-Related Variability in Decananometer MOSFETs With Conventional Architecture , 2007, IEEE Transactions on Electron Devices.

[15]  Subhash Saini,et al.  Hierarchical approach to "atomistic" 3-D MOSFET simulation , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  C Millar,et al.  Understanding LER-Induced MOSFET $V_{T}$ Variability—Part II: Reconstructing the Distribution , 2010, IEEE Transactions on Electron Devices.

[17]  Han-Ku Cho,et al.  Effect of line-edge roughness (LER) and line-width roughness (LWR) on sub-100-nm device performance , 2004, SPIE Advanced Lithography.

[18]  Christian Monzio Compagnoni,et al.  Comprehensive Investigation of Statistical Effects in Nitride Memories—Part I: Physics-Based Modeling , 2010, IEEE Transactions on Electron Devices.

[19]  G. Ghibaudo,et al.  Impact of grain number fluctuations in the MOS transistor gate on matching performance , 2003, International Conference on Microelectronic Test Structures, 2003..

[20]  Andrew R. Brown,et al.  Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs , 2003 .

[21]  A. Visconti,et al.  Physical modeling of single-trap RTS statistical distribution in flash memories , 2008, 2008 IEEE International Reliability Physics Symposium.

[22]  A. Asenov,et al.  Simulation of Statistical Aspects of Charge Trapping and Related Degradation in Bulk MOSFETs in the Presence of Random Discrete Dopants , 2010, IEEE Transactions on Electron Devices.

[23]  H. Tuinhout.  Impact of Parametric Fluctuations on Performance and Yield of Deep-Submicron Technologies , 2002, 32nd European Solid-State Device Research Conference.

[24]  A. Asenov,et al.  Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations , 2002 .

[25]  A Maconi,et al.  Comprehensive Investigation of Statistical Effects in Nitride Memories—Part II: Scaling Analysis and Impact on Device Performance , 2010, IEEE Transactions on Electron Devices.

[26]  Andrew R. Brown,et al.  Increase in the random dopant induced threshold fluctuations and lowering in sub-100 nm MOSFETs due to quantum effects: a 3-D density-gradient simulation study , 2001 .

[27]  Hong Yang,et al.  Reliability Issues and Models of sub-90nm NAND Flash Memory Cells , 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

[28]  Hyun-Woo Kim,et al.  Experimental investigation of the impact of LWR on sub-100-nm device performance , 2004, IEEE Transactions on Electron Devices.

[29]  A. Asenov,et al.  Analysis of Threshold Voltage Distribution Due to Random Dopants: A 100 000-Sample 3-D Simulation Study , 2009, IEEE Transactions on Electron Devices.

[30]  Krishna Parat,et al.  25nm 64Gb MLC NAND technology and scaling challenges invited paper , 2010, 2010 International Electron Devices Meeting.

[31]  G. Declerck.  A look into the future of nanoelectronics , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[32]  Donggun Park,et al.  Data retention characteristics of sub-100 nm NAND flash memory cells , 2003 .

[33]  Kinam Kim,et al.  Degradation of tunnel oxide by FN current stress and its effects on data retention characteristics of 90 nm NAND flash memory cells , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[34]  A. Asenov,et al.  Integrated atomistic process and device simulation of decananometre MOSFETs , 2002, International Conferencre on Simulation of Semiconductor Processes and Devices.

[35]  A. Asenov,et al.  Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness , 2003 .

[36]  A. Asenov,et al.  Impact of Fermi level pinning at polysilicon gate grain boundaries on nano-MOSFET variability: A 3-D simulation study , 2006, 2006 European Solid-State Device Research Conference.

[37]  A. Ghetti,et al.  Modeling the VTH fluctuations in nanoscale Floating Gate memories , 2008, 2008 International Conference on Simulation of Semiconductor Processes and Devices.

[38]  G. Ghibaudo,et al.  Degradation of floating-gate memory reliability by few electron phenomena , 2006, IEEE Transactions on Electron Devices.

[39]  G. Ghibaudo,et al.  Impact of a single grain boundary in the polycrystalline silicon gate on sub 100nm bulk MOSFET characteristics - Implication on matching properties , 2006 .