Efficient ROM size reduction for distributed arithmetic

In distributed arithmetic-based architecture for an inner product between two length N vectors, the size of the ROM increases exponentially with N. Moreover, the ROMs are generally the bottleneck of speed, especially when their size is large. In this paper, a ROM size reduction technique for DA (Distributed Arithmetic) is proposed. The proposed method is based on modified OBC (Offset Binary Coding) and a control circuit reduction technique. By simulations, it is shown that the use of the proposed technique can result in reduction in the number of gates by up 50%.