Modeling of electromigration in through-silicon-via based 3D IC

Electromigration (EM) is a critical problem for interconnect reliability of modern IC design, especially as the feature size becomes smaller. In 3D IC technology, the EM problem becomes more severe due to drastic dimension mismatches between metal wires, through-silicon-vias (TSVs), and landing pads. Meanwhile, the thermo-mechanical stress due to TSV can further interact with EM and shorten the lifetime of the structure. However, there is very little study on EM issues with respect to TSV for 3D ICs. In this paper, we perform detailed and systematic studies on: (1) EM lifetime modeling of TSV structure, (2) impact of TSV stress on EM lifetime of BEOL wires, and (3) EM-robust design guidelines for TSV-based 3D ICs. Our results show EM-induced lifetime of TSV structure and neighboring wire largely depend on the TSV-induced stress. Also, lifetime of a wire can vary significantly depending on the relative position with the nearby TSV.

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