Development of hybrid electrical model for CNT based Through Silicon Vias

This paper presents a hybrid electrical model of Carbon nanotube (CNT) based Through Silicon Via (TSV) using Metal Oxide Semiconductor (MOS) structural approach which takes into account factors such as substrate doping, operational frequency and voltage transmission levels. The MOS structural approach considers the CNT-based TSVs as a metal-oxide-semiconductor device, thereby resulting in a depletion capacitance which reduces the overall TSV capacitance. This affects the electrical performance of CNT-based TSVs, but has been ignored in previous models. Evaluation of electrical performance has been performed through S-parameter simulation of TSV and the simulation results have been compared with previously published electrical models of CNT-based TSV. The proposed hybrid electrical model shows CNT-based TSV better performance when compared with other published models.

[1]  S. Datta Electrical resistance: an atomistic view , 2004, cond-mat/0408319.

[2]  P. McEuen,et al.  Electron Transport in Single-Walled Carbon Nanotubes , 2004 .

[3]  Jun Li,et al.  Carbon Nanotube Based Interconnect Technology: Opportunities and Challenges , 2007 .

[4]  P. Burke,et al.  Microwave transport in metallic single-walled carbon nanotubes. , 2005, Nano letters.

[5]  P. Burke Luttinger liquid theory as a model of the gigahertz electrical properties of carbon nanotubes , 2002 .

[6]  Hsien-Hsin S. Lee,et al.  3D-MAPS: 3D Massively parallel processor with stacked memory , 2012, 2012 IEEE International Solid-State Circuits Conference.

[7]  Bruce C. Kim,et al.  Characterization of high performance CNT-based TSV for high-frequency RF applications , 2012 .

[8]  P. Ajayan,et al.  Reliability and current carrying capacity of carbon nanotubes , 2001 .

[9]  Kaustav Banerjee,et al.  Are carbon nanotubes the future of VLSI interconnections? , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[10]  R. Tummala,et al.  Rigorous Electrical Modeling of Through Silicon Vias (TSVs) With MOS Capacitance Effects , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[11]  W. Dehaene,et al.  Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs , 2010, IEEE Transactions on Electron Devices.

[12]  L. Delzeit,et al.  Electronic properties of multiwalled carbon nanotubes in an embedded vertical array , 2002 .

[13]  K. Ng,et al.  The Physics of Semiconductor Devices , 2019, Springer Proceedings in Physics.

[14]  M. Meyyappan,et al.  Bottom-up approach for carbon nanotube interconnects , 2003 .

[15]  A. R. Wazzan,et al.  MOS (Metal Oxide Semiconductor) Physics and Technology , 1986 .

[16]  Kaustav Banerjee,et al.  Performance analysis of carbon nanotube interconnects for VLSI applications , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[17]  Bruce C. Kim,et al.  Analysis of carbon nanotube based Through Silicon Vias , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[18]  M. Bockrath Carbon Nanotubes: Electrons in One Dimension , 1999 .

[19]  G. Duesberg,et al.  Carbon nanotubes for interconnect applications , 2002, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..