Mapping algorithms for a multi-bit data path processing reconfigurable chip RHW

While FPGAs are mainly used for implementing general purpose logic circuits, the RHW works with the CPU to accelerate the computation intensive part of the application by reconfiguring its data paths and ALUs optimized for the algorithm. Hence the RRW was designed to implement multi-bit data paths and ALUs efficiently. We developed a new architecture that consists of a two-dimensional array of multi-bit original ALU that is composed of a type of adder with multi-functional pre-logics.