Memory Fault Modeling Trends: A Case Study

In recent years, embedded memories are the fastest growing segment of system on chip. They therefore have a major impact on the overall Defect per Million (DPM). Further, the shrinking technologies and processes introduce new defects that cause previously unknown faults; such faults have to be understood and modeled in order to design appropriate test techniques that can reduce the DPM level. This paper discusses a new memory fault class, namely dynamic faults, based on industrial test results; it defines the concept of dynamic faults based on the fault primitive concept. It further shows the importance of dynamic faults for the new memory technologies and introduces a systematic way for modeling them. It concludes that current and future SRAM products need to consider testability for dynamic faults or leave substantial DPM on the table, and sets a direction for further research.

[1]  Sudhakar M. Reddy,et al.  A March Test for Functional Faults in Semiconductor Random Access Memories , 1981, IEEE Transactions on Computers.

[2]  Ravindra Nair.  Comments on "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories" , 1979, IEEE Trans. Computers.

[3]  Said Hamdioui,et al.  An experimental analysis of spot defects in SRAMs: realistic fault models and tests , 2000, Proceedings of the Ninth Asian Test Symposium.

[4]  A. J. van de Goor,et al.  Testing Semiconductor Memories: Theory and Practice , 1998 .

[5]  Zaid Al-Ars,et al.  Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests , 2003, J. Electron. Test..

[6]  Ad J. van de Goor,et al.  Approximating infinite dynamic behavior for DRAM cell defects , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[7]  Yervant Zorian,et al.  2001 Technology Roadmap for Semiconductors , 2002, Computer.

[8]  Mile K. Stojcev.  High Performance Memory Testing: Design Principles, Fault Modeling and Self-Test; R. Dean Adams, Kluwer Academic Publishers, Boston, 2003, Hardcover, pp 247, plus XIII, ISBN 1-4020-7255-4 , 2003, Microelectron. Reliab..

[9]  Ad J. van de Goor,et al.  Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[10]  NaikSamir,et al.  Failure Analysis of High-Density CMOS SRAMs , 1993 .

[11]  Zaid Al-Ars,et al.  Functional memory faults: a formal notation and a taxonomy , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[12]  Said Hamdioui,et al.  March SS: a test for all static simple RAM faults , 2002, Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002).

[13]  Melvin A. Breuer,et al.  Diagnosis and Reliable Design of Digital Systems , 1977 .

[14]  Said Hamdioui,et al.  Testing static and dynamic faults in random access memories , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[15]  Marian Marinescu,et al.  Simple and Efficient Algorithms for Functional RAM Testing , 1982, ITC.

[16]  Wojciech Maly,et al.  Failure analysis of high-density CMOS SRAMs: using realistic defect modeling and I/sub DDQ/ testing , 1993, IEEE Design & Test of Computers.

[17]  Ad J. van de Goor,et al.  Industrial evaluation of DRAM tests , 1999, DATE '99.

[18]  Frans P. M. Beenker,et al.  A realistic fault model and test algorithms for static random access memories , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Tom Chen,et al.  On comparing functional fault coverage and defect coverage for memory testing , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Magdy S. Abadir,et al.  Functional Testing of Semiconductor Random Access Memories , 1983, CSUR.

[21]  Carlos R. P. Hartmann,et al.  An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories , 1977, IEEE Transactions on Computers.