Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM
暂无分享,去创建一个
Francky Catthoor | Said Hamdioui | Mottaqiallah Taouil | Pieter Weckx | Stefan Cosemans | Daniel Kraak | Innocent Agbo
[1] Diana Marculescu,et al. Analysis of dynamic voltage/frequency scaling in chip-multiprocessors , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).
[2] Mehdi Baradaran Tahoori,et al. Aging mitigation in memory arrays using self-controlled bit-flipping technique , 2015, The 20th Asia and South Pacific Design Automation Conference.
[3] Said Hamdioui,et al. Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[4] B. Kaczer,et al. Analytic modeling of the bias temperature instability using capture/emission time maps , 2011, 2011 International Electron Devices Meeting.
[5] Francky Catthoor,et al. Read path degradation analysis in SRAM , 2016, 2016 21th IEEE European Test Symposium (ETS).
[6] G. Groeseneken,et al. Atomistic approach to variability of bias-temperature instability in circuit simulations , 2011, 2011 International Reliability Physics Symposium.
[7] Michael Nicolaidis,et al. Reliability challenges of real-time systems in forthcoming technology nodes , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[8] Francky Catthoor,et al. Degradation analysis of high performance 14nm FinFET SRAM , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[9] E. Seevinck,et al. Static-noise margin analysis of MOS SRAM cells , 1987 .
[10] Francky Catthoor,et al. Bias Temperature Instability analysis of FinFET based SRAM cells , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[11] B. Parvais,et al. Defect-based compact modeling for RTN and BTI variability , 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).
[12] Hao-I Yang,et al. Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.
[13] Rudy Lauwereins,et al. BTI reliability from planar to FinFET nodes: Will the next node be more or less reliable? , 2014 .
[14] Sreeram Chandrasekar,et al. Dynamic voltage (IR) drop analysis and design closure: Issues and challenges , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).
[15] Francky Catthoor,et al. Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations , 2015, ACM Comput. Surv..
[16] Sachin S. Sapatnekar,et al. Impact of NBTI on SRAM read stability and design for reliability , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).
[17] N. Horiguchi,et al. Response of a single trap to AC negative Bias Temperature stress , 2011, 2011 International Reliability Physics Symposium.
[18] Francky Catthoor,et al. Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[19] Ching-Te Chuang,et al. Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability , 2009, Microelectron. Reliab..
[20] Francky Catthoor,et al. Mitigation of sense amplifier degradation using input switching , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.
[21] Abhijit Chatterjee,et al. Device aging: A reliability and security concern , 2018, 2018 IEEE 23rd European Test Symposium (ETS).
[22] R. Degraeve,et al. Origin of NBTI variability in deeply scaled pFETs , 2010, 2010 IEEE International Reliability Physics Symposium.
[23] Kaushik Roy,et al. Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.
[24] Said Hamdioui,et al. Modeling and mitigating NBTI in nanoscale circuits , 2011, 2011 IEEE 17th International On-Line Testing Symposium.
[25] Hamid Mahmoodi,et al. Impact of transistor aging effects on sense amplifier reliability in nano-scale CMOS , 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).
[26] S. Natarajan,et al. High sigma measurement of random threshold voltage variation in 14nm Logic FinFET technology , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).
[27] Andrew R. Brown,et al. Impact of NBTI/PBTI on SRAM Stability Degradation , 2011, IEEE Electron Device Letters.
[28] Shekhar Y. Borkar. Microarchitecture and Design Challenges for Gigascale Integration , 2004, MICRO.
[29] Ilia Polian,et al. Analyzing the effects of peripheral circuit aging of embedded SRAM architectures , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.
[30] W. Dehaene,et al. Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies , 2006, IEEE Journal of Solid-State Circuits.
[31] Yu Cao,et al. Predictive Modeling of the NBTI Effect for Reliable Design , 2006, IEEE Custom Integrated Circuits Conference 2006.
[32] Francky Catthoor,et al. Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability , 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).