论文信息 - Layout strategy of P+ pick-up on the LV nMOST ESD reliability for 0.6μm to 0.18μm CMOS technologies

Layout strategy of P+ pick-up on the LV nMOST ESD reliability for 0.6μm to 0.18μm CMOS technologies

A multi-finger LV nMOST is often applied to the input/output pads as electrostatic discharge protection (ESD) elements. However, the non-uniform turned-on phenomenon always occurred, i.e. these sub-nMOSTs can't be turned-on simultaneously. The ESD current will be passed through a few turned-on MOSTs. It was due to the RB resistance of parasitic bipolar transistor for each finger transistor in silicon bulk region is quite different. In this paper, the P+ pick-up area in source-side influence on the protection components in ESD capability of input/output pads will be investigated for 0.6μm to 0.18μm CMOS technologies. Here, the best stripe number choice of P+ pick-up will be carried out the important snapback parameters. We focus on exploring the value of secondary breakdown current (It2) and some physical parameters for the ESD robustness. Hopefully, it does effectively enhance ESD capability to solve the exactly non-uniform turned-on issue.

Shen-Li Chen | Min-Hua Lee

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