Self-repairing mobile robotic car using astrocyte-neuron networks

A self-repairing robot utilising a spiking astrocyte-neuron network is presented in this paper. It uses the output spike frequency of neurons to control the motor speed and robot activation. A software model of the astrocyte-neuron network previously demonstrated self-detection of faults and its self-repairing capability. In this paper the application demonstrator of mobile robotics is employed to evaluate the fault-tolerant capabilities of the astrocyte-neuron network when implemented in a hardware-based robotic car system. Results demonstrated that when 20% or less synapses associated with a neuron are faulty, the robot car can maintain system performance and complete the task of forward motion correctly. If 80% synapses are faulty, the system performance shows a marginal degradation, however this degradation is much smaller than that of conventional fault-tolerant techniques under the same levels of faults. This is the first time that astrocyte cells merged within spiking neurons demonstrates a self-repairing capabilities in the hardware system for a real application.

[1]  Jim Harkin,et al.  Fault-Tolerant Networks-on-Chip Routing With Coarse and Fine-Grained Look-Ahead , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  K. Chakrabarty,et al.  Towards fault-tolerant digital microfluidic lab-on-chip: Defects, fault modeling, testing, and reconfiguration , 2008, 2008 IEEE Biomedical Circuits and Systems Conference.

[3]  Tobi Delbrück,et al.  Using FPGA for visuo-motor control with a silicon retina and a humanoid robot , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[4]  Liam McDaid,et al.  Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers , 2012, Neural Networks.

[5]  Tobi Delbrück,et al.  CAVIAR: A 45k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory–Processing– Learning–Actuating System for High-Speed Visual Object Recognition and Tracking , 2009, IEEE Transactions on Neural Networks.

[6]  Jim Harkin,et al.  Online traffic-aware fault detection for networks-on-chip , 2014, J. Parallel Distributed Comput..

[7]  Jim Harkin,et al.  Low Overhead Monitor Mechanism for Fault-Tolerant Analysis of NoC , 2014, 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs.

[8]  Liam McDaid,et al.  Bio-Inspired Online Fault Detection in NoC Interconnect , 2014 .

[9]  Liam McDaid,et al.  On the role of astroglial syncytia in self-repairing spiking neural networks , 2015, IEEE Transactions on Neural Networks and Learning Systems.

[10]  Liam McDaid,et al.  Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations , 2013, IEEE Transactions on Parallel and Distributed Systems.

[11]  N. Brunel,et al.  Astrocytes: Orchestrating synaptic plasticity? , 2015, Neuroscience.

[12]  Marco Wiering,et al.  2011 INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS (IJCNN) , 2011, IJCNN 2011.

[13]  Jim Harkin,et al.  Low cost fault-tolerant routing algorithm for Networks-on-Chip , 2015, Microprocess. Microsystems.

[14]  Bernabé Linares-Barranco,et al.  Multicasting Mesh AER: A Scalable Assembly Approach for Reconfigurable Neuromorphic Structured AER Systems. Application to ConvNets , 2013, IEEE Transactions on Biomedical Circuits and Systems.

[15]  Liam McDaid,et al.  Self-repair in a bidirectionally coupled astrocyte-neuron (AN) system based on retrograde signaling , 2012, Front. Comput. Neurosci..

[16]  Zhai Zhang,et al.  Method to self-repairing reconfiguration strategy selection of embryonic cellular array on reliability analysis , 2014, 2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[17]  M. Domínguez-Morales,et al.  A Neuro-Inspired Spike-Based PID Motor Controller for Multi-Motor Robots with Low Cost FPGAs , 2012, Sensors.

[18]  Martin Trefzer,et al.  PAnDA: A Reconfigurable Architecture that Adapts to Physical Substrate Variations , 2013, IEEE Transactions on Computers.

[19]  Pasi Liljeberg,et al.  Analysis of forward error correction methods for nanoscale networks-on-chip , 2007, Nano-Net.

[20]  Liam McDaid,et al.  Case study: Bio-inspired self-adaptive strategy for spike-based PID controller , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[21]  Tien-Hsin Chao,et al.  Integration of the reconfigurable self-healing eDNA architecture in an embedded system , 2011, 2011 Aerospace Conference.

[22]  Itsuo Takanami,et al.  A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network , 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[23]  Wulfram Gerstner,et al.  SPIKING NEURON MODELS Single Neurons , Populations , Plasticity , 2002 .

[24]  Kening Zhang,et al.  Triple Modular Redundancy with Standby (TMRSB) Supporting Dynamic Resource Reconfiguration , 2006, 2006 IEEE Autotestcon.

[25]  Tetsu Tanaka,et al.  A 37 × 37 pixels artificial retina chip with edge enhancement function for 3-D stacked fully implantable retinal prosthesis , 2012, 2012 IEEE Biomedical Circuits and Systems Conference (BioCAS).

[26]  Irith Pomeranz,et al.  Robust Fault Models Where Undetectable Faults Imply Logic Redundancy , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.