A study on buffer distribution for RRAM-based FPGA routing structures

Compared to Application-Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) provide reconfigurablity at the cost of lower performance and higher power consumption. Exploiting a large number of programmable switches, routing structures are mainly responsible for the performance limitation. Hence, employing more efficient switches can drastically improve the performance and reduce the power consumption of the FPGA. Resistive Random Access Memory (RRAM)-based switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. The lower RC delay of RRAM-based routing multiplexers, as compared to CMOS-based routing structures encourages us to reconsider the buffer distribution in FPGAs. This paper proposes an approach to reduce the number of buffers in the routing path of RRAM-based FPGAs. Our architectural simulations show that the use of RRAM switches improves the critical path delay by 56% as compared to CMOS switches in standard FPGA circuits at 45-nm technology node while, at the same time, the area and power are reduced, respectively, by 17% and 9%. By adapting the buffering scheme, an extra bonus of 9% for delay reduction, 5% for power reduction and 16% for area reduction can be obtained, as compared to the conventional buffering approach for RRAM-based FPGAs.

[1]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[2]  Wei Wang,et al.  rFGA: CMOS-nano hybrid FPGA using RRAM components , 2008, 2008 IEEE International Symposium on Nanoscale Architectures.

[3]  B. Gao,et al.  A Physics-Based Compact Model of Metal-Oxide-Based RRAM DC and AC Operations , 2013, IEEE Transactions on Electron Devices.

[4]  G. De Micheli,et al.  Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs , 2013, IEEE Transactions on Nanotechnology.

[5]  S. Yang,et al.  Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .

[6]  Meng-Fan Chang,et al.  A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes , 2013, IEEE Journal of Solid-State Circuits.

[7]  Kenneth B. Kent,et al.  The VTR project: architecture and CAD for FPGAs from verilog to routing , 2012, FPGA '12.

[8]  Jason Cong,et al.  FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[10]  Heng-Yuan Lee,et al.  A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability , 2011, 2011 IEEE International Solid-State Circuits Conference.

[11]  Fabien Clermidy,et al.  Emerging memory technologies for reconfigurable routing in FPGA architecture , 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

[12]  Yusuf Leblebici,et al.  GMS: Generic memristive structure for non-volatile FPGAs , 2012, 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

[13]  Mingjie Lin,et al.  A Low-Power Field-Programmable Gate Array Routing Fabric , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Fabien Clermidy,et al.  Using OxRRAM memories for improving communications of reconfigurable FPGA architectures , 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures.

[15]  Abbas El Gamal,et al.  Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory , 2012, 2012 IEEE International Solid-State Circuits Conference.

[16]  Duane Mills,et al.  19.7 A 16Gb ReRAM with 200MB/s write and 1GB/s read in 27nm technology , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).