Compiler-Architecture Exploration using Reservation Tables Generation

Contemporary processors with wide parallelism and deep pipelines result in complex and intrinsically nonstructured interactions between different architectural features of the processor, the compiler and the application, making it extremely difficult to predict performance variations when changing different processor features. Compiler-Architecture Co-Exploration is required to evaluate the effects of architectural changes (such as connectivity sharing) on the performance of the entire system. These architectural modifications require the specification of detailed resource conflict information (generally represented as Reservation Tables) to the compiler – a task traditionally done manually on a per-operation basis. However, for deep pipelines, with complex resource sharing, and large non-structured instruction sets, manual, per-operation specification is a very tedious and error prone task. Moreover, reflecting the changes to the architecture during exploration in the conflict information requires changes to many Reservation Tables. In this paper we present a technique for automatic generation of Reservation Tables, that is used to drive architectural exploration of a large number of designs. Since the designer is relieved from the burden of manual specification and updating, he can drive fast exploration iterations, and cover a large space of architectures. We briefly outline our automatic Reservation Tables generation approach, and present a set of exploration experiments on a large set of EPIC architectures, for varying connectivity sharing, number of functional units, multicycling units, with varied latency configurations. For each point in the architecture space we evaluate a set of benchmarks from scientific, multimedia and general purpose application domains. Our experiments demonstrate that such a compiler-architecture exploration environment can uncover many interesting and non-intuitive architectural design points, giving the system designer flexibility to perform further system-level tradeoffs.