A flexible formal verification framework for industrial scale validation

In recent years, leading microprocessor companies have made huge investments to improve the reliability of their products. Besides expanding their validation and CAD tools teams, they have incorporated formal verification methods into their design flows. Formal verification (FV) engineers require extensive training, and FV tools from CAD vendors are expensive. At first glance, it may seem that FV teams are not affordable by smaller companies. We have not found this to be true. This paper describes the formal verification framework we have built on top of publicly-available tools. This framework gives us the flexibility to work on myriad different problems that occur in microprocessor design.

[1]  Roope Kaivola,et al.  Formal Verification of the Pentium® 4 Floating-Point Multiplier , 2002, DATE.

[2]  Aaron R. Bradley,et al.  SAT-Based Model Checking without Unrolling , 2011, VMCAI.

[3]  Anna Slobodov Challenges for formal verification in industrial setting , 2006 .

[4]  Panagiotis Manolios,et al.  Computer-Aided Reasoning: An Approach , 2011 .

[5]  Randal E. Bryant,et al.  Boolean Analysis of MOS Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Panagiotis Manolios,et al.  Computer-aided reasoning : ACL2 case studies , 2000 .

[7]  Anna Slobodová,et al.  Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation , 2009, CAV.

[8]  Sofia Cassel,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 2012 .

[9]  David M. Russinoff A Case Study in Fomal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD AthlonTM Processor , 2000, FMCAD.

[10]  Bishop Brock,et al.  The Verification of a Bit-slice ALU , 1989, Hardware Specification, Verification and Synthesis.

[11]  Robert S. Boyer,et al.  Symbolic simulation in ACL2 , 2009, ACL2 '09.

[12]  Anna Slobodová Challenges for Formal Verification in Industrial Setting , 2006, FMICS/PDMC.

[13]  Anna Slobodová Formal Verification of Hardware Support for Advanced Encryption Standard , 2008, 2008 Formal Methods in Computer-Aided Design.

[14]  A. Kuehlmann,et al.  Equivalence Checking Using Cuts And Heaps , 1997, Proceedings of the 34th Design Automation Conference.

[15]  David S. Hardin Design and Verification of Microprocessor Systems for High-Assurance Applications , 2010 .

[16]  Robert K. Brayton,et al.  Efficient implementation of property directed reachability , 2011, 2011 Formal Methods in Computer-Aided Design (FMCAD).

[17]  David M. Russinoff A Mechanically Checked Proof of IEEE Compliance of the Floating Point Multiplication, Division and Square Root Algorithms of the AMD-K7™ Processor , 1998, LMS J. Comput. Math..

[18]  Carl-Johan H. Seger,et al.  Formal verification using parametric representations of Boolean constraints , 1999, DAC '99.

[19]  Sol Otis Swords A verified framework for symbolic execution in the ACL2 theorem prover , 2010 .

[20]  Sol Swords,et al.  Centaur Technology Media Unit Verification , 2009, CAV.

[21]  Warren A. Hunt,et al.  Verifying VIA Nano microprocessor components , 2010, Formal Methods in Computer Aided Design.

[22]  Kenneth L. McMillan,et al.  Interpolation and SAT-Based Model Checking , 2003, CAV.

[23]  Alan Mishchenko,et al.  A single-instance incremental SAT formulation of proof- and counterexample-based abstraction , 2010, Formal Methods in Computer Aided Design.

[24]  E. Clarke,et al.  Symbolic model checking using SAT procedures instead of BDDs , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[25]  Carl-Johan H. Seger,et al.  A Methodology for Large-Scale Hardware Verification , 2000, FMCAD.

[26]  Robert S. Boyer,et al.  Function memoization and unique object representation for ACL2 functions , 2006, ACL2 '06.

[27]  Jason Baumgartner,et al.  Automatic formal verification of fused-multiply-add FPUs , 2005, Design, Automation and Test in Europe.