An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS
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R. Krishnamurthy | A. Agarwal | S. Borkar | M. Anders | S. Mathew | S. Hsu
[1] P. Bai,et al. A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
[2] Atila Alvandpour,et al. A burn-in tolerant dynamic circuit technique , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).
[3] Jeffrey L. Miller,et al. 7-4 A 16GB/s, 0.18p.m Cache Tile for Integrated L2 Caches from 256KB to 2MB. , 2000 .
[4] Lei Wang,et al. The multi-threaded, parity-protected 128-word register files on a dual-core Itanium/sup /spl reg//-family processor , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..