An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS

A 16times64b 1R/1W register file is fabricated in 65nm CMOS technology. The 0.017mm2 chip performs 8.8GHz fused decode and read/write operations in a single cycle while dissipating 198mW at 1.2V, 50degC, with frequency scalable to 10.1GHz at 1.4V, 50degC. Variation-tolerant keeper compensation, leakage-tolerant BL/WL architecture and optimal non-minimum channel-length usage enable wide PVT operating range with an active leakage of 25mW and a BL noise droop les8mV

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