Reducing Variation in Advanced Logic Technologies

[1]  A. Asenov.  Simulation of Statistical Variability in Nano MOSFETs , 2007, 2007 IEEE Symposium on VLSI Technology.

[2]  T. Fukai,et al.  SRAM critical yield evaluation based on comprehensive physical / statistical modeling, considering anomalous non-Gaussian intrinsic transistor fluctuations , 2007, 2007 IEEE Symposium on VLSI Technology.

[3]  Kaushik Roy,et al.  Process Variations and Process-Tolerant Design , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[4]  Eric S. Fetzer.  Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design , 2006, IEEE Design & Test of Computers.

[5]  Y. Momiyama,et al.  Direct Evaluation of Gate Line Edge Roughness Impact on Extension Profiles in Sub-50-nm n-MOSFETs , 2006, IEEE Transactions on Electron Devices.

[6]  H. Kimura,et al.  RTA-Driven Intra-Die Variations in Stage Delay, and Parametric Sensitivities for 65nm Technology , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[7]  G. Dewey,et al.  Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[8]  E.J. Nowak,et al.  Modeling of Variation in Submicrometer CMOS ULSI Technologies , 2006, IEEE Transactions on Electron Devices.

[9]  Luigi Capodieci.  From optical proximity correction to lithography-driven physical design (1996-2006): 10 years of resolution enhancement technology and the roadmap enablers for the next decade , 2006, SPIE Advanced Lithography.

[10]  Shekhar Y. Borkar,et al.  Designing reliable systems from unreliable components: the challenges of transistor variability and degradation , 2005, IEEE Micro.

[11]  Kaushik Roy,et al.  Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits , 2005, IEEE Journal of Solid-State Circuits.

[12]  N. Vallepalli,et al.  SRAM design on 65nm CMOS technology with integrated leakage reduction scheme , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[13]  V. Macary,et al.  Current mismatch due to local dopant fluctuations in MOSFET channel , 2003 .

[14]  A. Asenov,et al.  Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations , 2002 .

[15]  T. Tanaka,et al.  Vth fluctuation induced by statistical variation of pocket dopant profile , 2000 .

[16]  A. Dengi,et al.  A two-dimensional low pass filter model for die-level topography variation resulting from chemical mechanical polishing of ILD films , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[17]  A. Ghetti,et al.  Severe thickness variation of sub-3 nm gate oxide due to Si surface faceting, poly-Si intrusion, and corner stress , 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

[18]  S. Nassif,et al.  Modeling the effects of manufacturing variation on high-speed microprocessor interconnect performance , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[19]  A. Asenov.  Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFET's: A 3-D "atomistic" simulation study , 1998 .

[20]  P. Stolk,et al.  Modeling statistical dopant fluctuations in MOS transistors , 1998 .

[21]  Chunyan Zhou,et al.  Accurate on-chip interconnect evaluation: a time domain technique , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[22]  J. R. Brews,et al.  Surface Potential Fluctuations Generated by Interface Charge Inhomogeneities in MOS Devices , 1972 .