论文信息 - A 140MS/s 10-bit pipelined ADC with a folded S/H stage

A 140MS/s 10-bit pipelined ADC with a folded S/H stage

A 140MS/s 10-bit pipelined analog-to-digital converter (ADC) using a folded sample-and-hold (S/H) stage and a 5-bit flash ADC is presented. To conquer the limited linear swing range results from an operational amplifier (OP-AMP). The proposed folded S/H stage allows the ADC to operate in the linear swing range of an OP-AMP. Only 17 comparators are required for a 5-bit flash ADC. Corresponding digital correction codes are added. The single-phase triggering method is adopted and it saves half the number of shift/latch elements. This pipelined ADC has been fabricated in a 0.18um CMOS process. It dissipates 65mW for a supply voltage of 1.8V. The measured signal-to-noise-plus-distortion ratio (SNDR) is achieved 55.4 dB. The differential nonlinearity (DNL) and integral nonlinearity (INL) is 0.78-LSB and 0.98-LSB, respectively.

Shen-Iuan Liu | Hwei-Yu Lee

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