Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks
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Sylvain Guilley | Jean-Luc Danger | Laurent Fesquet | Laurent Sauvage | Taha Beyrouthy | Sumanta Chaudhuri
[1] George S. Taylor,et al. Improving smart card security using self-timed circuits , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.
[2] Kiyoshi Oguri,et al. Asynchronous Circuit Design , 2001 .
[3] Xinmiao Zhang,et al. Wireless Security and Cryptography: Specifications and Implementations , 2007 .
[4] Thomas Roche,et al. Multi-Linear cryptanalysis in Power Analysis Attacks MLPA , 2009, ArXiv.
[5] Jean-Jacques Quisquater,et al. Physically Secure Cryptographic Computations: From Micro to Nano Electronic Devices , 2007 .
[6] George S. Taylor,et al. Balanced self-checking asynchronous logic for smart card applications , 2003, Microprocess. Microsystems.
[7] Sylvain Guilley,et al. Practical Setup Time Violation Attacks on AES , 2008, 2008 Seventh European Dependable Computing Conference.
[8] Sylvain Guilley,et al. WDDL is Protected against Setup Time Violation Attacks , 2009, 2009 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC).
[9] Sylvain Guilley,et al. Security Evaluation of a Balanced Quasi-Delay Insensitive Library (SecLib) , 2008 .
[10] Paul C. Kocher,et al. Differential Power Analysis , 1999, CRYPTO.
[11] Guido Bertoni,et al. Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks , 2008, IEEE Transactions on Computers.