Electrical validation of source synchronous chip-chip server links at 6.25 Gb/s

Modeling and validation of 6.25 Gb/s source synchronous backplane links is demonstrated using a correlation methodology. The link model predictions correlate within 10-25% error against scope measured eye and using on-die scope eye when the transmitter output jitter, the interconnect loss and impedance profile and the transmitter equalizer is well modeled and correlated individually. In this paper, the link is assumed to have only transmitted side de-emphasis (equalization). The procedure get additional confidence, when the eye, created from the internal timing and voltage margins, correlates within 10-25% error to the predicted data pad eye. With these a reasonably scalable model over different topologies/speeds that can be used confidently for sensitivity analysis and predictions is obtained.