Identifying defects in deep-submicron CMOS ICs

With safety margins for reliability, test, failure analysis, and design verification shrinking, it would be a shame to give up the I/sub DDQ/ technique-and luckily, we may not have to. Steps can be taken to maintain its applicability as we rush deeper into the submicron regime. We will first examine why the I/sub DDQ/ test serves several interests, then describe the challenge posed by 0.35-0.07 μm transistor geometries, and finally propose several solutions.