In-line total overlay measurement to operate tools beyond their capability

Lithography is plagued by variations in critical dimensions and alignment. Both parameters contribute to the total overlay of one layer to the previous one. In the past, we had the luxury of using additive techniques to figure total overlay budget. Now circuit patterns have shrunken to the point that if we design a chip by adding errors, we would no longer be able to make anything. Designers today use the root mean square (RMS) of the errors to figure the spec. In turn the Process Engineer must adapt to this by finding new techniques to maintain CDs and alignment. Measuring total overlay, using statistics and RMS, we can continue to produce chips beyond the presumed capability of our tools. Measurements for CDs and alignment are fed forward to the next masking step, combined with the CDs and alignment at that step to calculate the total overlay and spec satisfaction. Using this method, parameters that may be beyond your process capability can be judged based on their electrical impact.