ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs

Built-in self-repair (BISR) technique has been widely used to repair embedded random access memories (RAMs). This paper presents a reconfigurable BISR (ReBISR) scheme for repairing RAMs with different sizes and redundancy organizations. An efficient redundancy analysis algorithm is proposed to allocate redundancies of defective RAMs. In the ReBISR, a reconfigurable built-in redundancy analysis (ReBIRA) circuit is designed to perform the redundancy algorithm for various RAMs. Also, an adaptively reconfigurable fusing methodology is proposed to reduce the repair setup time when the RAMs are operated in normal mode. Experimental results show that the ReBISR scheme can achieve high repair rate (i.e., the ratio of the number of repaired RAMs to the number of defective RAMs). The area cost of the ReBISR is very small, which is only about 2.7% for four RAMs (one 4 Kbit RAM, one 16 Kbit RAM, one 128 Kbit RAM, and one 512 Kbit RAM). Moreover, the time overhead of redundancy analysis is very small. For example, the ratio of the redundancy analysis time to the test time for a 512 Kbit RAM tested by a March-14 test with solid data backgrounds is only about 0.25%. On the other hand, the proposed fusing scheme can achieve about 86.94% reduction of repair setup time in comparison with a typical fusing scheme for 20 512 × 16 × 64-bit RAMs of which each RAM has one spare row and one spare column.

[1]  Jin-Fu Li,et al.  Built-in redundancy analysis for memory yield improvement , 2003, IEEE Trans. Reliab..

[2]  Chi-Yi Hwang,et al.  A Hierarchical Test Methodology for Systems on Chip , 2002, IEEE Micro.

[3]  Dilip K. Bhavsar.  An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264 , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[4]  Jin-Fu Li,et al.  A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs , 2008, 2008 IEEE International Test Conference.

[5]  Keiichi Higeta,et al.  Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[6]  Yu-Jen Huang,et al.  A Built-in Self-repair Scheme for Multiport Rams , 2022 .

[7]  W. Kent Fuchs,et al.  Efficient Spare Allocation for Reconfigurable Arrays , 1987 .

[8]  Cheng-Wen Wu,et al.  An integrated ECC and redundancy repair scheme for memory reliability enhancement , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[9]  Joseph Rayhawk,et al.  At-speed built-in self-repair analyzer for embedded word-oriented memories , 2004, 17th International Conference on VLSI Design. Proceedings..

[10]  Jin-Fu Li,et al.  A built-in self-repair design for RAMs with 2-D redundancy , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Yervant Zorian,et al.  Embedded-memory test and repair: infrastructure IP for SoC yield , 2003, IEEE Design & Test of Computers.

[12]  Rochit Rajsuman.  Design and Test of Large Embedded Memories: An Overview , 2001, IEEE Des. Test Comput..

[13]  Alfredo Benso,et al.  An on-line BIST RAM architecture with self-repair capabilities , 2002, IEEE Trans. Reliab..

[14]  Francky Catthoor,et al.  Guest Editors' Intoduction: The New World of Large Embedded Memories , 2001, IEEE Des. Test Comput..

[15]  Steven F. Oakland,et al.  On-chip repair and an ATE independent fusing methodology , 2002, Proceedings. International Test Conference.

[16]  Jin-Fu Li,et al.  A simulator for evaluating redundancy analysis algorithms of repairable embedded memories , 2002, Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002).

[17]  Jin-Fu Li,et al.  Raisin: Redundancy Analysis Algorithm Simulation , 2007, IEEE Design & Test of Computers.

[18]  Michael R. Ouellette,et al.  Shared fuse macro for multiple embedded memory devices with redundancy , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[19]  Steven F. Oakland,et al.  An on-chip self-repair calculation and fusing methodology , 2003, IEEE Design & Test of Computers.

[20]  Shyue-Kung Lu,et al.  Efficient built-in redundancy analysis for embedded memories with 2-D redundancy , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  Jin-Fu Li,et al.  A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[22]  Yervant Zorian,et al.  Built in self repair for embedded high density SRAM , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[23]  Nadir Achouri,et al.  Optimal reconfiguration functions for column or data-bit built-in self-repair , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[24]  Rubin A. Parekhji,et al.  On-chip Test and Repair of Memories for Static and Dynamic Faults , 2006, 2006 IEEE International Test Conference.

[25]  Jin-Fu Li,et al.  Memory fault diagnosis by syndrome compression , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[26]  W. Kent Fuchs,et al.  Efficient Spare Allocation in Reconfigurable Arrays , 1986, 23rd ACM/IEEE Design Automation Conference.

[27]  Yervant Zorian.  Embedded Memory Test & Repair : Infrastructure IP for SOC Yield Yervant Zorian Virage Logic , 2002 .

[28]  Hideto Hidaka,et al.  A built-in self-repair analyzer (CRESTA) for embedded DRAMs , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[29]  M. Nicolaidis,et al.  Dynamic Data-bit Memory Built-In Self- Repair , 2003, ICCAD 2003.

[30]  Steffen Paul,et al.  Memory built-in self-repair using redundant words , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[31]  Hans-Joachim Wunderlich,et al.  An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy , 2007, 12th IEEE European Test Symposium (ETS'07).

[32]  Cheng-Wen Wu,et al.  A processor-based built-in self-repair design for embedded memories , 2003, 2003 Test Symposium.

[33]  Jin-Fu Li,et al.  A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs , 2006, 2006 IEEE International Test Conference.

[34]  Jin-Fu Li,et al.  ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[35]  Cheng-Wen Wu,et al.  Raisin: Redundancy Analysis Algorithm Simulation , 2007 .

[36]  Jin-Fu Li,et al.  An Infrastructure IP for Repairing Multiple RAMs in SOCs , 2006, 2006 International Symposium on VLSI Design, Automation and Test.