AN IMPLEMENTATIONTECHNIQUEOF MULTI-CYCLEDARITHMETICFUNCTIONS FOR A DYNAMICALLYRECONFIGURABLEPROCESSOR

Dynamically Reconfigurable Processor (DRP) released by NEC Electronics is expected to have potential for high de­ gree of parallel processing. Applications for DRP are de­ scribed in C language, and parallelism in the source code is automatically extracted by a compiler. On the other hand, it is also important to optimize descriptions so that the po­ tential performance of the device is effectively brought out. In this paper, arithmetic algorithms and an optimized coding technique to efficiently implement applications with multi­ cycled arithmetic functions on DRP are discussed, focus­ ing on the required number of the states. In this technique, the same kind of multi-cycled functions are aggregated into single functions, and arithmetic algorithms whose behav­ ior is steady on operand values are utilized. The effects of the technique are evaluated with fixed-point arithmetic func­ tions and polynomial arithmetic functions over a finite field, showing 2.68",,3.09 times performance improvement with­ out large increase in the number of states nor severe degra­ dation of the frequency.