Scaling beyond the 65 nm node with FinFET-DGCMOS
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Joachim Keinert | David M. Fried | Matthew J. Breitwisch | Thomas Ludwig | J. Kedzierski | Edward J. Nowak | Beth Ann Rainey | Ingo Dr Aller | M. Leong | V. Gemhoefer | M. Breitwisch | E. Nowak | J. Kedzierski | B. Rainey | D. Fried | T. Ludwig | I. Aller | M. Leong | J. Keinert | V. Gemhoefer
[1] D. Hisamoto,et al. A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET , 1989, International Technical Digest on Electron Devices Meeting.
[2] C. Hu,et al. Nanoscale CMOS spacer FinFET for the terabit era , 2002 .
[3] R. Chau,et al. Advanced depleted-substrate transistors: Single-gate, double-gate, and Tri-gate , 2002 .
[4] J. Kedzierski,et al. Demonstration of FinFET CMOS circuits , 2002, 60th DRC. Conference Digest Device Research Conference.
[5] Y. Yeo,et al. 25 nm CMOS Omega FETs , 2002, Digest. International Electron Devices Meeting,.
[6] J. Kedzierski,et al. A functional FinFET-DGCMOS SRAM cell , 2002, Digest. International Electron Devices Meeting,.
[7] E. Nowak,et al. High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
[8] Bin Yu,et al. FinFET scaling to 10 nm gate length , 2002, Digest. International Electron Devices Meeting,.
[9] T.C. Holloway,et al. A new edge-defined approach for submicrometer MOSFET fabrication , 1981, IEEE Electron Device Letters.
[10] J. Bokor,et al. FinFET-a quasi-planar double-gate MOSFET , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).