CMOS ADC-based receivers for high-speed electrical and optical links

CMOS ADC-based serial link receivers enable powerful digital equalization and symbol detection techniques for high data rate operation over electrical and optical wireline channels. Common ADC architectures and equalization techniques that allow 10 Gb/s and higher operation are surveyed in this article. As time-interleaving is most often employed to achieve these high sampling rates, the associated errors and calibration techniques are presented. The impact of ADC quantization noise on receiver performance and how this can be improved via embedded partial analog equalization are detailed. A description of a 65 nm CMOS hybrid ADC-based receiver architecture that employs a 3-tap analog FFE embedded inside a 6-bit asynchronous successive approximation register (SAR) ADC and a per-symbol dynamically enabled digital equalizer operating at 10 Gb/s concludes the discussion.

[1]  Samuel Palermo,et al.  A 25GS/s 6b TI binary search ADC with soft-decision selection in 65nm CMOS , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

[2]  Samuel Palermo,et al.  A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization , 2016, IEEE Journal of Solid-State Circuits.

[3]  Yusuf Leblebici,et al.  Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS , 2016, IEEE Journal of Solid-State Circuits.

[4]  Wei Zhang,et al.  A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber , 2010, IEEE Journal of Solid-State Circuits.

[5]  Thomas Krause,et al.  A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  Ian Dedic.  56Gs/s ADC : Enabling 100GbE , 2010, 2010 Conference on Optical Fiber Communication (OFC/NFOEC), collocated National Fiber Optic Engineers Conference.

[7]  Thomas Toifl,et al.  A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology , 2012, IEEE Journal of Solid-State Circuits.

[8]  Lawrence T. Pileggi,et al.  A 69.5 mW 20 GS/s 6b Time-Interleaved ADC With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI , 2014, IEEE Journal of Solid-State Circuits.

[9]  Yong Liu,et al.  3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[10]  Chih-Kong Ken Yang,et al.  Power Optimized ADC-Based Serial Link Receiver , 2012, IEEE Journal of Solid-State Circuits.

[11]  Bo Zhang,et al.  3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOS , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[12]  Song-Hee Paik,et al.  A 10.3-GS/s, 6-Bit Flash ADC for 10G Ethernet Applications , 2013, IEEE Journal of Solid-State Circuits.

[13]  Jorge Pernillo,et al.  3.4 A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOS , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[14]  Elad Alon,et al.  A 6b 46GS/s ADC with >23GHz BW and sparkle-code error correction , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

[15]  Bo Zhang,et al.  A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5–11.5 Gb/s Serial Links , 2015, IEEE Journal of Solid-State Circuits.