Folded Cascode Amplifying Structure Evaluation in terms of the used IC process in Radiation Detection Front End Applications

The charge sensitive amplifier (CSA) unit is used in processing signals from capacitive sensors such as photo-detectors, pressure sensors, particle and X-ray detectors. Next generation front-end ASICs will use advanced CMOS and BiCMOS technologies including MOSFETs with minimum channel length (of 45 nm and below) and SiGe Heterojunction Bipolar Transistors (HBTs). The most common CSA architecture employed either in CMOS or BiCMOS implementations is the folded cascode amplifying topology due to its low noise performance, the high gain capability and its gain insensitivity to the detector capacitance variations [1]-[4]. While noise optimization methodologies have been proposed for both kinds of CSAs (CMOS or BiCMOS) and plenty of CSA designs were so far presented [1]–[5], none extended research has been performed about the suitability of each process in relation to the application specifications such as detector capacitance, power consumption, noise performance and speed. In addition, other important issues like the main noise contributors and the radiation hardness capability are also not have been extensively addressed. Particularly, four equivalent folded cascode amplifying topologies were designed. The primary concern was the examination of devices noise contribution, firstly the input transitor and cascoded one and secondary the reset device noise contribution. The four structures were: a) nMOS as the input and pMOS as cascode, b) pMOS as input, nMOS as cascode, c) npn BJT as input, pMOS as cascode and d) pMOS as input and npn BJT as cascode. To further isolate these noise contributors, ideal bias current sources and output buffer were used, in all four designs. Feedback was implemented using a capacitance in parallel with a large reset resistor. The structures were designed using specific noise optimization criteria – design methodologies [1], [5]-[6] in two respective processes commercially available by Austria Mikro Systeme (AMS), the 0.35μm CMOS process (2P/3M 3.3/5V) and the 0.35μm SiGe BiCMOS process (2P/3M 3.3/5V). All four folded cascode topologies are depicted in figure 1.