Squash: a scalable quantum mapper considering ancilla sharing

Quantum algorithms for solving problems of interesting size often result in circuits with a very large number of qubits and quantum gates. Fortunately, these algorithms also tend to contain a small number of repetitively-used quantum kernels. Identifying the quantum logic blocks that implement such quantum kernels is critical to the complexity management for realizing the corresponding quantum circuit. Moreover, quantum computation requires some type of quantum error correction coding to combat decoherence, which in turn results in a large number of ancilla qubits in the circuit. Sharing the ancilla qubits among quantum operations (even though this sharing can increase the overall circuit latency) is important in order to curb the resource demand of the quantum algorithm. This paper presents a multi-core reconfigurable quantum processor architecture, called Requp, which supports a layered approach to mapping a quantum algorithm and ancilla sharing. More precisely, a scalable quantum mapper, called Squash, is introduced, which divides a given quantum circuit into a number of quantum kernels--each kernel comprises k parts such that each part will run on exactly one of k available cores. Experimental results demonstrate that Squash can handle large-scale quantum algorithms while providing an effective mechanism for sharing ancilla qubits.

[1]  John Kubiatowicz,et al.  A fault tolerant, area efficient architecture for Shor's factoring algorithm , 2009, ISCA '09.

[2]  Yu-Chin Hsu,et al.  A formal approach to the scheduling problem in high level synthesis , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Massoud Pedram,et al.  LEQA: Latency estimation for a quantum algorithm mapped to a quantum circuit fabric , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[4]  Igor L. Markov,et al.  On the CNOT-cost of TOFFOLI gates , 2008, Quantum Inf. Comput..

[5]  Archil Avaliani,et al.  Quantum Computers , 2004, ArXiv.

[6]  Mark Oskin,et al.  Microcoded Architectures for Ion-Tap Quantum Computers , 2008, 2008 International Symposium on Computer Architecture.

[7]  Thierry Paul,et al.  Quantum computation and quantum information , 2007, Mathematical Structures in Computer Science.

[8]  Frederic T. Chong,et al.  Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

[9]  Salvador Elías Venegas-Andraca,et al.  Quantum Walks for Computer Scientists , 2008, Quantum Walks for Computer Scientists.

[10]  Vipin Kumar,et al.  Multilevel Algorithms for Multi-Constraint Graph Partitioning , 1998, Proceedings of the IEEE/ACM SC98 Conference.

[11]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[12]  Daniel A. Spielman,et al.  Exponential algorithmic speedup by a quantum walk , 2002, STOC '03.

[13]  R. V. Meter,et al.  Layered architecture for quantum computing , 2010, 1010.5022.

[14]  Margaret Martonosi,et al.  ScaffCC: a framework for compilation and analysis of quantum computing programs , 2014, Conf. Computing Frontiers.

[15]  Andrew W. Cross,et al.  Transversality Versus Universality for Additive Quantum Codes , 2007, IEEE Transactions on Information Theory.

[16]  Andrew W. Cross,et al.  A quantum logic array microarchitecture: scalable quantum data movement and computation , 2005, 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05).

[17]  Osamu Tatebe,et al.  Workflow Scheduling to Minimize Data Movement Using Multi-constraint Graph Partitioning , 2012, 2012 12th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (ccgrid 2012).

[18]  Alireza Shafaei,et al.  Design of a universal logic block for fault-tolerant realization of any logic operation in trapped-ion quantum circuits , 2014, Quantum Information Processing.

[19]  Massoud Pedram,et al.  Minimizing the latency of quantum circuits during mapping to the ion-trap circuit fabric , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).