论文信息 - A low-power RISC microprocessor using dual PLLs in a 0.13 /spl mu/m SOI technology with copper interconnect and low-k BEOL dielectric

A low-power RISC microprocessor using dual PLLs in a 0.13 /spl mu/m SOI technology with copper interconnect and low-k BEOL dielectric

Microprocessors achieving clock frequencies >1 GHz for mobile applications require solutions to maintain long battery life. Circuit and architecture solutions for dynamic frequency switching between multiple PLLs, DC power reduction methods, and impact of low-k dielectric on timing and power are discussed.

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