What is Bet-Hedging
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An improved synchronizer for recovering the clock signal in split phase encoded data. The synchronizer includes a phase locked loop (PLL) which locks in phase with the encoded data at twice the data clock frequency. The output from the PLL is divided by two in a flip flop which is triggerable to produce an output at either 0 DEG or 180 DEG relative phase. The encoded data is detected in synchronism with the output of the flip flop and the resultant is integrated over each cycle of the flip flop signal. Comparator circuitry produces an error signal if the integrated value is within predetermined limits. A counter receives the error signals and, in response to a significant number thereof, activates the flip flop to produce its alternate phase output. In this manner, the flip flop output recovers the clock signal in proper phase.