ASIP DESIGN METHODOLOGIES

[1]  Rainer Leupers,et al.  Retargetable generation of code selectors from HDL processor models , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[2]  Hugo De Man,et al.  Instruction set definition and instruction selection for ASIPs , 1994, Proceedings of 7th International Symposium on High-Level Synthesis.

[3]  T. C. May,et al.  Instruction-set matching and selection for DSP and ASIP code generation , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[4]  A. Alomary,et al.  An ASIP instruction set optimization algorithm with functional module sharing constraint , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[5]  P. Faraboschi,et al.  An evaluation system for application specific architectures , 1990, [1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture.

[6]  Miodrag Potkonjak,et al.  Power efficient mediaprocessors: design space exploration , 1999, DAC '99.

[7]  Jan Rabaey,et al.  Retargetable estimation scheme for DSP architecture selection , 2000, ASP-DAC '00.

[8]  Gary William Grewal,et al.  An integrated approach to retargetable code generation , 1994, Proceedings of 7th International Symposium on High-Level Synthesis.

[9]  Ing-Jer Huang,et al.  Synthesis of application specific instruction sets , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Rainer Leupers,et al.  Instruction selection for embedded DSPs with complex instructions , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[11]  B. Wess,et al.  A retargetable optimizing code generator for digital signal processors , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[12]  Dilip K. Banerji,et al.  Instruction-set matching and GA-based selection for embedded-processor code generation , 1996, Proceedings of 9th International Conference on VLSI Design.

[13]  Alexandru Nicolau,et al.  Performance evaluation for application-specific architectures , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[14]  Hugo De Man,et al.  A graph based processor model for retargetable code generation , 1996, Proceedings ED&TC European Design and Test Conference.

[15]  Masaharu Imai,et al.  An integrated design environment for application specific integrated processor , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[16]  Ed F. Deprettere,et al.  The construction of a retargetable simulator for an architecture template , 1998, CODES.