Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity

A 3.2-Gbit/sec 2048-bit parallel LDPC decoder is implemented in a 0.18 /spl mu/m CMOS process. We employ two new techniques to address the interconnect problem: A broadcasting technique reduces the total amount of check-to-variable interconnect wires by more than 40%. A hierarchical placement algorithm places the variable and check nodes in the top-level hierarchy of the design and reduces the maximum wire length by up to 50%.

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