论文信息 - Correction to "A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS" [Mar 11 660-668]

Correction to "A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS" [Mar 11 660-668]

In Sec. III-A of the above titled paper (ibid., vol. 46, no. 3, pp. 660-668, Mar. 2011), paper [2}, which presents a similar compensation technique to that presented in [1], should have been cited. The authors would like to thank Prof. Saxena for informing us about this missing reference.

Mohammad Taherzadeh-Sani | Anas A. Hamoui

[1] Mohammad Taherzadeh-Sani,et al. A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS , 2011, IEEE Journal of Solid-State Circuits.

[2] V. Saxena,et al. Compensation of CMOS op-amps using split-length transistors , 2008, 2008 51st Midwest Symposium on Circuits and Systems.