A Review Paper on Design of Positive Edge Triggered D Flip-Flop using VLSI Technology

A Delay (D) flip-flop is an edge triggering device. A high speed, low power consumption, positive edge triggered Delay (D) flip-flop can be designed for increasing the speed of counter in Phase locked loop, using VLSI technology. The designed counter can be used in the divider chip of the phase locked loop. A divide counter is required in the feedback loop to increase the VCO frequency above the input reference frequency. The propose circuit will be faster than conventional circuit as it will be a fast reset operation. The circuit will be consuming less power as it prevents short circuit power

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