Clique partitioning based integrated architecture synthesis for VLSI chips

Tasks such as module selection, scheduling and allocation involved in the architecture synthesis problem of VLSI chips are tightly interdependent. Simultaneous optimization of these tasks is necessary for the global solution of a design. The authors present a new graph model for the integrated architecture synthesis problem of VLSI chips and then formulate the problem as a partial clique partition problem and solve it globally using a heuristic. The approach has been tested using examples from the literature and experimental results show that it is better then or as good as other published approaches.<<ETX>>

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