A BiNoC architecture - aware task allocation and communication scheduling scheme

Abstract A novel real-time task allocation and scheduling scheme is proposed for a multi-core system incorporated in a Bidirectional Network-on-Chip (BiNoC) platform. Given a task graph, this scheme seeks to minimize the total execution time by allocating ready-to-execute tasks to as many available cores as possible subject to the real-time deadlines of each task. A refinement process is introduced to update the priority ranking of a task list so as to meet the timing constraints. In particular, the communication overhead is considered by incorporating the packet routing paths and delays into the overall optimization process. In doing so, the flexibility of bidirectional links of BiNoC is exploited to alleviate traffic congestion, such that more tasks could be executed concurrently at different cores and overall execution time be reduced. To validate the effectiveness of this proposed scheme, extensive simulations have been performed. The results clearly demonstrate the superior performance of this proposed scheme compared to existing approaches that did not exploit the flexibility of BiNoC.

[1]  Salim Hariri,et al.  Performance-Effective and Low-Complexity Task Scheduling for Heterogeneous Computing , 2002, IEEE Trans. Parallel Distributed Syst..

[2]  Yu Hen Hu,et al.  QoS aware BiNoC architecture , 2010, 2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS).

[3]  Edward A. Lee,et al.  A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures , 1993, IEEE Trans. Parallel Distributed Syst..

[4]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[5]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[6]  Kang G. Shin,et al.  Improvement of Real-Time Multi-CoreSchedulability with Forced Non-Preemption , 2014, IEEE Transactions on Parallel and Distributed Systems.

[7]  Yu Hen Hu,et al.  3D Bidirectional-Channel Routing Algorithm for Network-Based Many-Core Embedded Systems , 2013, EMC/HumanCom.

[8]  Bashir M. Al-Hashimi,et al.  Considering power variations of DVS processing elements for energy minimisation in distributed systems , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

[9]  Yu Hen Hu,et al.  A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable Channel , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Emmanuel Jeannot,et al.  Comparative Evaluation Of The Robustness Of DAG Scheduling Heuristics , 2008, CoreGRID Integration Workshop.

[11]  Yu Hen Hu,et al.  A Fault-Tolerant NoC Scheme using bidirectional channel , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[12]  ArabnejadHamid,et al.  List Scheduling Algorithm for Heterogeneous Systems by an Optimistic Cost Table , 2014 .

[13]  Hamid Arabnejad,et al.  List Scheduling Algorithm for Heterogeneous Systems by an Optimistic Cost Table , 2014, IEEE Transactions on Parallel and Distributed Systems.

[14]  Petru Eles,et al.  An approach to incremental design of distributed embedded systems , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[15]  Radu Marculescu,et al.  Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[16]  Wayne H. Wolf,et al.  TGFF: task graphs for free , 1998, Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98).

[17]  Axel Jantsch,et al.  Networks on chip , 2003 .

[18]  Hamid Arabnejad,et al.  Performance Evaluation of List Based Scheduling on Heterogeneous Systems , 2011, Euro-Par Workshops.

[19]  Yuan Xie,et al.  Allocation and scheduling of conditional task graph in hardware/software co-synthesis , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[20]  Petru Eles,et al.  Energy-efficient mapping and scheduling for DVS enabled distributed embedded systems , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[21]  Vivek Sarkar,et al.  Partitioning and Scheduling Parallel Programs for Multiprocessing , 1989 .

[22]  Yu Hen Hu,et al.  BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[23]  Radu Marculescu,et al.  Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization , 2003, ICCAD 2003.

[24]  Neil W. Bergmann,et al.  A Hardware Scheduler Based on Task Queues for FPGA-Based Embedded Real-Time Systems , 2015, IEEE Transactions on Computers.

[25]  Jean Jyh-Jiun Shann,et al.  ETAHM: An energy-aware task allocation algorithm for heterogeneous multiprocessor , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[26]  William J. Dally.  Computer Architecture in the Many-Core Era , 2006, 2006 International Conference on Computer Design.

[27]  Gang Qu,et al.  CASPER: an integrated energy-driven approach for task graph scheduling on distributed embedded systems , 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

[28]  Coniferous softwood.  GENERAL TERMS , 2003 .