A reconfigurable FFT architecture for variable-length and multi-streaming OFDM standards

This paper presents a reconfigurable FFT architecture for variable-length and multi-streaming WiMax wireless standard. The architecture processes 1 stream of 2048-point FFT, up to 2 streams of 1024-point FFT or up to 4 streams of 512-point FFT. The architecture consists of a modified radix-2 single delay feedback (SDF) FFT. The sampling frequency of the system is varied in accordance with the FFT length. The latch-free clock gating technique is used to reduce power consumption. The proposed architecture has been synthesized for the Virtex-6 XCVLX760 FPGA. Experimental results show that the architecture achieves the throughput that is required by the WiMax standard and the design has additional features compared to the previous approaches. The design uses 1% of the total available FPGA resources and maximum clock frequency of 313.67 MHz is achieved. Furthermore, this architecture can be expanded to suit other wireless standards.

[1]  Keshab K. Parhi,et al.  A Pipelined FFT Architecture for Real-Valued Signals , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Xiaoyang Zeng,et al.  A 128/256-point pipeline FFT/IFFT processor for MIMO OFDM system IEEE 802.16e , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[3]  Jong-Won Park,et al.  Design of FFT processor for IEEE802.16m MIMO-OFDM systems , 2010, 2010 International Conference on Information and Communication Technology Convergence (ICTC).

[4]  Axel Wenzler,et al.  New structures for complex multipliers and their noise analysis , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[5]  Song-Nien Tang,et al.  An Area- and Energy-Efficient Multimode FFT Processor for WPAN/WLAN/WMAN Systems , 2012, IEEE Journal of Solid-State Circuits.

[6]  S.-W. Chen,et al.  A High-speed Highly Pipelined 2N-point FFT Architecture For A Dual Ofdm Processor , 2006, Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006..

[7]  Jesús Grajal,et al.  Accurate Rotations Based on Coefficient Scaling , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[8]  Mario Garrido Gálvez.  Efficient hardware architectures for the computation of the FFT and other related signal processing algorithms in real time , 2009 .

[9]  Chen-Yi Lee,et al.  A 2.4-Gsample/s DVFS FFT Processor for MIMO OFDM Communication Systems , 2008, IEEE Journal of Solid-State Circuits.

[10]  Jesús Grajal,et al.  Optimum Circuits for Bit Reversal , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  Viktor Öwall,et al.  Architectures for Dynamic Data Scaling in 2/4/8K Pipeline FFT Cores , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Jesús Grajal,et al.  Pipelined Radix-$2^{k}$ Feedforward FFT Architectures , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Shousheng He,et al.  Design and implementation of a 1024-point pipeline FFT processor , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[14]  Oscar Gustafsson,et al.  A 512-point 8-parallel pipelined feedforward FFT for WPAN , 2011, 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR).