On cache memory hierarchy for Chip-Multiprocessor

Advances in integrated circuit technology have led the microprocessor design to more challenging areas by providing a high budget of transistors. The one billion microprocessor is not that far from now. This leads microarchitects to look for efficient ways to make use of this feature. Chip-Multiprocessor (CMP) is one of the strong candidates in this area. Memory system for any multiprocessor is a pivotal part and can boost the performance or decrease it dramatically. The purpose of this study is to investigate the most appropriate cache memory hierarchy for CMP. We provide comparisons between several candidates and present a conclusion that can lead to better performance for CMP as well as the configurations that must be avoided.

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