Sequential synthesis for table look up PGAs

The algorithms for synthesis onto programmable gate arrays (PGAs) have so far addressed only the combinational logic problem. The authors present two algorithms for mapping a sequential circuit onto a specific table look up architecture, namely the Xilinx 3090 architecture. The first algorithm maps combinational and sequential elements simultaneously. In the second, combinational elements are mapped first, followed by the sequential elements. The combinational synthesis techniques are used to solve the sequential synthesis problem.<<ETX>>