Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders

Standard VLSI implementations of turbo decoding require substantial memory and incur a long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for low-latency turbo decoding, comprising multiple single-input single-output (SISO) elements, operating jointly on one turbo-coded block, is presented and compared to sequential architectures. A parallel interleaver is essential to process multiple concurrent SISO outputs. A novel parallel interleaver and an algorithm for its design are presented, achieving the same error correction performance as the standard architecture. Latency is reduced up to 20 times and throughput for large blocks is increased up to six-fold relative to sequential decoders, using the same silicon area, and achieving a very high coding gain. The parallel architecture scales favorably: latency and throughput are improved with increased block size and chip area.

[1]  Peter A. Beerel,et al.  A low latency SISO with application to broadband turbo decoding , 2001, IEEE J. Sel. Areas Commun..

[2]  Branka Vucetic,et al.  A code-matched interleaver design for turbo codes , 2002, IEEE Trans. Commun..

[3]  Sergio Benedetto,et al.  Mapping interleaving laws to parallel turbo decoder architectures , 2004, IEEE Communications Letters.

[4]  A. Giulietti,et al.  Parallel turbo coding interleavers: avoiding collisions in accesses to storage elements , 2002 .

[5]  Daesik Hong,et al.  An implementation method of a turbo-code decoder using a block-wise MAP algorithm , 2000, Vehicular Technology Conference Fall 2000. IEEE VTS Fall VTC2000. 52nd Vehicular Technology Conference (Cat. No.00CH37152).

[6]  John Cocke,et al.  Optimal decoding of linear codes for minimizing symbol error rate (Corresp.) , 1974, IEEE Trans. Inf. Theory.

[7]  Jakob Dahl Andersen.  SELECTION OF CODE AND INTERLEAVER FOR TURBO CODING , 1998 .

[8]  Jah-Ming Hsu,et al.  A parallel decoding scheme for turbo codes , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[9]  V. Derudder,et al.  A scalable 8.7nJ/bit 75.6Mb/s parallel concatenated convolutional (turbo-) CODEC , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[10]  T. Giles,et al.  Improving the constituent codes of turbo encoders , 1998, IEEE GLOBECOM 1998 (Cat. NO. 98CH36250).

[11]  V. Derudder,et al.  A 80 Mb/s low-power scalable turbo codec core , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

[12]  Stephen B. Wicker,et al.  Turbo Coding , 1998 .

[13]  Ran Ginosar,et al.  Parallel VLSI architecture for MAP turbo decoder , 2002, The 13th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications.

[14]  Yeheskel Bar-Ness,et al.  A parallel MAP algorithm for low latency turbo decoding , 2002, IEEE Communications Letters.

[15]  S. Golomb,et al.  Constructions and properties of Costas arrays , 1984, Proceedings of the IEEE.

[16]  Norbert Wehn,et al.  Concurrent interleaving architectures for high-throughput channel coding , 2003, 2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03)..

[17]  Keshab K. Parhi,et al.  Area-efficient high speed decoding schemes for turbo/MAP decoders , 2001, 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221).

[18]  Keshab K. Parhi,et al.  Area-efficient high-speed decoding schemes for turbo decoders , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[19]  Alain Glavieux,et al.  Reflections on the Prize Paper : "Near optimum error-correcting coding and decoding: turbo codes" , 1998 .

[20]  Massimo Ruo Roch,et al.  VLSI architectures for turbo codes , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[21]  Norbert Wehn,et al.  A Scalable System Architecture for High-Throughput Turbo-Decoders , 2005, J. VLSI Signal Process..

[22]  Heinrich Meyr,et al.  Real-time algorithms and VLSI architectures for soft output MAP convolutional decoding , 1995, Proceedings of 6th International Symposium on Personal, Indoor and Mobile Radio Communications.

[23]  Ran Ginosar,et al.  Parallel VLSI Architecture and Parallel Interleaver Design for Low-Latency MAP Turbo Decoders , 2003 .

[24]  A. Glavieux,et al.  Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1 , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.