Digital relay protection testing device

The utility model relates to a digital relay protection testing device which comprises a central processing unit CPU, a complex programmable logic device CPLD, a memory, a field programmable gate array FPGA, a universal asynchronous receiver/transmitter UART, a kilomega fiber Ethernet module and an electric Ethernet module. The memory is a Flash memory and a DDR2 memory. The digital relay protection testing device is characterized in that the CPU is respectively connected with the CPLD, the DDR2 memory, the universal asynchronous receiver/transmitter UART, the FPGA and the electric Ethernet module; the flash memory is connected with the CPLD; and the FPGA is connected with the kilomega fiber Ethernet module. The digital relay protection testing device provided by the utility model can output the number of SMV control blocks, the number of SMV control block channels and the SMV control block frequency, and determines the scale of a simulated power system.