Analysis and optimization of LUDMOS transistors on a 0.18µm SOI CMOS technology

This paper is focused on the design and optimization of power LDMOS transistors (V<inf>BR</inf> ≫ 120 Volts) with the purpose of being integrated in a new generation of Smart Power technology based upon a 0.18 µm SOI-CMOS technology. The benefits of applying the shallow trench isolation (STI) concept along with the 3D RESURF concept in the LDMOS drift region is analyzed in terms of the main static (R<inf>on-sp</inf>/V<inf>BR</inf> trade-off) and dynamic (Miller capacitance and Q<inf>g</inf>×R<inf>on</inf> FOM) characteristics. The influence of some design parameters such as the polysilicon gate electrode length and the STI length are exhaustively analyzed.

[1]  Yung C. Liang,et al.  Superjunction LDMOS with drift region charge-balanced by distributed hexagon p-islands , 2003, 2003 IEEE Conference on Electron Devices and Solid-State Circuits (IEEE Cat. No.03TH8668).

[3]  C.A.T. Salama,et al.  150-V class superjunction power LDMOS transistor switch on SOI , 2002, Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics.

[4]  D. Flores,et al.  Analysis of low-voltage super-junction LDMOS structures on thin-SOI substrates , 2008 .

[5]  Shuming Xu,et al.  120 V interdigitated-drain LDMOS (IDLDMOS) on SOI substrate breaking power LDMOS limit , 2000 .

[6]  D. Flores,et al.  Static and dynamic electrical performances of STI thin-SOI power LDMOS transistors , 2008 .

[7]  Yuming Bai,et al.  Low-voltage superjunction technology , 2007, IET Circuits Devices Syst..

[8]  T. Fujihira.  Theory of Semiconductor Superjunction Devices , 1997 .

[9]  Yung C. Liang,et al.  Practical superjunction MOSFET device performance under given process thermal cycles , 2004 .

[10]  F. Morancho,et al.  A new lateral power MOSFET for smart power ICs: the “LUDMOS concept” , 1999 .

[11]  T. Uesugi,et al.  A concept of SOI RESURF lateral devices with striped trench electrodes , 2005, IEEE Transactions on Electron Devices.

[12]  A. Heringa,et al.  Extended (180 V) voltage in 0.6 /spl mu/m thin-layer-SOI A-BCD3 technology on 1 /spl mu/m BOX for display, automotive and consumer applications , 2002, Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics.