AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects

Small delay defects, when escaping from traditional delay testing, could cause a device to malfunction in the field. To address this issue, we propose an adaptive-frequency test method, abbreviated as AF-test. In this method, versatile test clocks can be generated on the chip by embedding an All-Digital Phase-Locked Loop (ADPLL) into the circuit under test (CUT). Instead of measuring the exact propagation delay associated with each test pattern like previous time-consuming failing frequency signature based analysis [14], we test only up to three different test clock frequencies for each test pattern to provide the benefit of fast characterization, and thereby making it suitable for volume production test. We have successfully demonstrated the AF-test on an in-house wireless test platform called HOY system using fabricated chips. This method can not only detect small delay defects effectively but also provide a grading scheme for those marginal chips that might have the reliability problem.

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